1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a semiconductor memory device including redundancy cells for replacing repair target memory cells.
2. Description of the Related Art
In general, a semiconductor memory device including Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM) has a large number of memory cells. Recently, as the integration degree of semiconductor memory devices increases with the development of process technology, the number of memory cells has been further increased. When a failure occurs in any one of the memory cells, the semiconductor memory device including the memory cell may not perform a desired operation. Thus, the semiconductor memory device must be discarded. Recently, however, with the development in the process technology of semiconductor memory devices, a failure occurs only in a small number of memory cells. Thus, if the entire semiconductor memory device is discarded as a defective product due to the failure in the small number of memory cells, it is very inefficient in terms of the yield of products. To resolve such a concern, the semiconductor memory device additionally includes redundancy memory cells as well as normal memory cells.
The redundancy memory cell may replace a normal memory cell in which a failure occurred (hereafter, referred to as ‘repair target memory cell’). More specifically, when a repair target memory cell is accessed during a read/write operation, a redundancy memory cell is accessed instead of the repair target memory cell. Thus, when an address corresponding to the repair target memory cell is inputted, the semiconductor memory device performs an operation for accessing the redundancy memory cell instead of the repair target memory cell. Hereafter, such operation will be referred to as ‘repair operation’. Through the repair operation, a normal operation of the semiconductor memory device is guaranteed.
In order to perform the repair operation, the semiconductor memory device requires circuits other than the redundancy memory cells. The circuits may include a repair fuse circuit. The repair fuse circuit includes a plurality of fuses for storing an address corresponding to a repair target memory cell. Hereafter, the address will be referred to as ‘repair target address’. Each fuse is programmed with a bit of a repair target address. At this time, programming indicates a series of operations for storing state information in a fuse. For example, programming may indicate an operation of storing a bit of a repair target address in a fuse. The semiconductor memory device performs a repair operation on a defective memory cell (i.e., a repair target memory cell), using repair target addresses programmed in a plurality of fuses.
The method for programming state information in a fuse may be divided into a physical method and an electrical method.
The physical method cuts a fuse by blowing the fuse using a laser beam according to state information to be programmed. The fuse is referred to as a physical type fuse. Since the fuse is cut by a laser beam, the fuse may also be referred to as a laser blowing type fuse. The physical type fuse can perform a programming operation in a wafer state before a semiconductor memory device is packaged, but cannot perform a programming operation in a package state.
The electrical method changes the connection state of a fuse by applying an over-current to the fuse according to state information to be programmed. The fuse is referred to as an electrical type fuse. The electrical type fuse may include an anti-type fuse and a rupture type fuse. The anti-type fuse changes an open state to a short state, and the rupture type fuse changes a short state to an open state, The electrical type fuse can perform a program ing operation even in a package state, unlike the physical type fuse.
A semiconductor memory device passes through a large number of test operations before the semiconductor memory device is commercialized, and only those that pass through all of the test operations are sold to a consumer. The test operations verify whether a test target circuit (e.g., a semiconductor memory device) operates normally. The test operations are conducted at each of the fabrication steps such that a failure which occurs at a particular fabrication step can be detected immediately, thereby preventing the addition of unnecessary fabrication costs. Thus, it is very important to detect a failure at the initial stage of the fabrication process.
At the package step, a test operation for normal memory cells and redundancy memory cells is performed. This operation includes a normal test operation for the normal memory cells and a redundancy test operation for the redundancy memory cells. The normal test operation can be performed on both the normal memory cells, and the redundancy memory cells that are replaced with repair target memory cells included in the normal cell region. Thus, during the redundancy test operation, another test may be performed on the redundancy memory cells that are replaced with the repair target memory cells. As test stress increases due to the duplicate tests on the redundancy memory cells replaced with the repair target memory cells, a stress imbalance between the cells may occur.